Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Some programmable ICs include hardwired microprocessors on the same chip or in the same package as the programmable interconnect and programmable logic and are sometimes referred to as a system on a chip (SoC). Applications built on SoCs will generally include numerous connections between the microprocessor, programmable logic, and memory and peripheral resources. The connections may be implemented as a number of interconnect busses.
There are different sizes of interconnect busses in many applications, and upsizer and downsizer circuits are used to transition between the different bus sizes. For some applications, such as safety systems, detection of errors on the interconnect buses may be critical. However, the interconnect busses may be implemented using logic provided by third parties, making it unfeasible to modify the bus interconnect circuitry to detect errors.